The disclosure relates to a semiconductor circuit design device, and can be applied to a circuit design device of a nonvolatile memory device incorporated in a semiconductor device.
Japanese Unexamined Patent Application Publication No. 2004-164035 discloses an integrated circuit design device and an integrated circuit design method that can design an integrated circuit at a high speed without performing high order synthesis.
“Microchip Technology Inc., serial EEPROM Verilog model, 11xx010 Verilog Model.zip, M11AA010.v, Internet <URL:http://www.microchip.com/ja/design-centers/memory/serial-eeprom/ve rilog-ibis-models>, the retrieval date: Nov. 25, 2016” discloses a serial EEPROM Verilog model. In the model, the states of a plurality of memory cells are simultaneously set using the FOR LOOP sentence as described in lines 1106 to 1125 of M11AA010.v in “Microchip Technology Inc., serial EEPROM Verilog model, 11xx010 Verilog Model.zip, M11AA010.v, Internet <URL:http://www.microchip.com/ja/design-centers/memory/serial-eeprom/ve rilog-ibis-models>, the retrieval date: Nov. 25, 2016”.